MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 962

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug support (DBG)
29.8
29.8.1
29.8.2
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Table 201. 32-bit debug port registers addressed through the shifted value A[3:2]
SW debug port
SW protocol introduction
This synchronous serial protocol uses two pins:
●
●
The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 K
recommended by ARM).
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.
SW protocol sequence
Each sequence consist of three phases:
1.
2.
3.
Address A(3:2) value
0xC
0x0
0x4
0x8
SWCLK: clock from host to target
SWDIO: bidirectional
Packet request (8 bits) transmitted by the host
Acknowledge response (3 bits) transmitted by the target
Data transfer phase (33 bits) transmitted by the host or the target
00
01
10
11
Reserved
DP CTRL/STAT register. Used to:
– Request a system or debug power-up
– Configure the transfer operation for AP accesses
– Control the pushed compare and pushed verify operations.
– Read some status flags (overrun, power-up acknowledges)
DP SELECT register: Used to select the current access port and the
active 4-words register window.
– Bits 31:24: APSEL: select the current AP
– Bits 23:8: reserved
– Bits 7:4: APBANKSEL: select the active 4-words register window on the
– Bits 3:0: reserved
DP RDBUFF register: Used to allow the debugger to get the final result
after a sequence of operations (without requesting new JTAG-DP
operation)
current AP
Doc ID 13902 Rev 9
Description
RM0008