MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 839

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
27.2.2
27.2.3
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DMA features
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PTP features
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Option to filter all error frames on reception and not forward them to the application in
Store-and-Forward mode
Option to forward under-sized good frames
Supports statistics by generating pulses for frames dropped or corrupted (due to
overflow) in the Receive FIFO
Supports Store and Forward mechanism for transmission to the MAC core
Automatic generation of PAUSE frame control or back pressure signal to the MAC core
based on Receive FIFO-fill (threshold configurable) level
Handles automatic retransmission of Collision frames for transmission
Discards frames on late collision, excessive collisions, excessive deferral and underrun
conditions
Software control to flush Tx FIFO
Calculates and inserts IPv4 header checksum and TCP, UDP, or ICMP checksum in
frames transmitted in Store-and-Forward mode
Supports internal loopback on the MII for debugging
Supports all AHB burst types in the AHB Slave Interface
Software can select the type of AHB burst (fixed or indefinite burst) in the AHB Master
interface.
Option to select address-aligned bursts from AHB master port
Optimization for packet-oriented DMA transfers with frame delimiters
Byte-aligned addressing for data buffer support
Dual-buffer (ring) or linked-list (chained) descriptor chaining
Descriptor architecture, allowing large blocks of data transfer with minimum CPU
intervention;
each descriptor can transfer up to 8 KB of data
Comprehensive status reporting for normal operation and transfers with errors
Individual programmable burst size for Transmit and Receive DMA Engines for optimal
host bus utilization
Programmable interrupt options for different operational conditions
Per-frame Transmit/Receive complete interrupt control
Round-robin or fixed-priority arbitration between Receive and Transmit engines
Start/Stop modes
Current Tx/Rx Buffer pointer as status registers
Current Tx/Rx Descriptor pointer as status registers
Received and transmitted frames time stamping
Coarse and fine correction methods
Trigger interrupt when system time becomes greater than target time
Pulse per second output (product alternate function output)
Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 9
839/995