MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 971

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
29.15.4
29.16
29.16.1
Table 209. Main ETM registers
Configuration example
To output a simple value to the TPIU:
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MCU debug component (MCUDBG)
The MCU debug component helps the debugger provide support for:
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Debug support for low-power modes
To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock
or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.
0xE0041FB0 ETM Lock Access
0xE004101C ETM Trace Enable Control This register defines which comparator is selected.
0xE0041000 ETM Control
0xE0041010 ETM Status
0xE0041008 ETM Trigger Event
0xE0041020 ETM Trace Enable Event
0xE0041024 ETM Trace Start/Stop
Address
Configure the TPIU and enable the I/IO_TRACEN to assign TRACE I/Os in the high-
density device’s debug configuration register
Write 0xC5ACCE55 to the ETM Lock Access Register to unlock the write access to the
ITM registers
Write 0x00001D1E to the control register (configure the trace)
Write 0000406F to the Trigger Event register (define the trigger event)
Write 0000006F to the Trace Enable Event register (define an event to start/stop)
Write 00000001 to the Trace Start/stop register (enable the trace)
Write 0000191E to the ETM Control Register (end of configuration)
Low-power modes
Clock control for timers, watchdog, I2C and bxCAN during a breakpoint
Control of the trace pins assignment
Register
Doc ID 13902 Rev 9
This register defines the trace enabling event.
Write 0xC5ACCE55 to unlock the write acess to the other
ETM registers.
This register controls the general operation of the ETM,
for instance how tracing is enabled.
This register provides information about the current status
of the trace and trigger logic.
This register defines the event that will control trigger.
This register defines the traces used by the trigger source
to start and stop the trace, respectively.
Details
Debug support (DBG)
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