MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 315

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bits 9:8 LOCK[1:0]: Lock configuration
Bit 13 BKP: Break polarity
Bit 12 BKE: Break enable
Bit 11 OSSR: Off-state selection for Run mode
Bit 10 OSSI: Off-state selection for Idle mode
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
0: Break input BRK is active low
1: Break input BRK is active high
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details
capture/compare enable register (TIMx_CCER) on page
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1. Then, OC/OCN enable output signal=1
This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details
capture/compare enable register (TIMx_CCER) on page
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
register, as long as the related channel is configured in output through the CCxS bits) as well
as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIMx_CCMRx registers, as long as the related channel is configured in output through the
CCxS bits) can no longer be written.
in TIMx_BDTR register).
TIMx_BDTR register).
bits in TIMx_BDTR register).
bits in TIMx_BDTR register).
has been written, their content is frozen until the next reset.
Doc ID 13902 Rev 9
Advanced-control timers (TIM1&TIM8)
(Section 13.4.9: TIM1&TIM8
(Section 13.4.9: TIM1&TIM8
308).
308).
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