MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 618

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial peripheral interface (SPI)
23.5.4
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Bits 15:0 DR[15:0]: Data register
Bit 3 UDR: Underrun flag
Bit 2 CHSIDE: Channel side
Bit 1 TXE: Transmit buffer empty
Bit 0 RXNE: Receive buffer not empty
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SPI data register (SPI_DR)
Address offset: 0x0C
Reset value: 0x0000
Notes for the SPI mode:
Note: Not used in SPI mode
Note: Not used for the SPI mode
Data received or to be transmitted.
The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading
(Receive buffer). A write to the data register will write into the Tx buffer and a read from the data
register will return the value held in the Rx buffer.
0: No underrun occurred
1: Underrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
for the software sequence.
0: Tx buffer not empty
1: Tx buffer empty
0: Rx buffer empty
1: Rx buffer not empty
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0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
Depending on the data frame format selection bit (DFF in SPI_CR1 register), the data sent or
received is either 8-bit or 16-bit. This selection has to be made before enabling the SPI to
ensure correct operation.
For an 8-bit data frame, the buffers are 8-bit and only the LSB of the register (SPI_DR[7:0]) is
used for transmission/reception. When in reception mode, the MSB of the register
(SPI_DR[15:8]) is forced to 0.
For a 16-bit data frame, the buffers are 16-bit and the entire register, SPI_DR[15:0] is used for
transmission/reception.
No meaning in PCM mode
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9
Doc ID 13902 Rev 9
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DR[15:0]
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6
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5
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4
Section 23.4.7 on page 613
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2
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RM0008
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