MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 674

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal synchronous asynchronous receiver transmitter (USART)
Note:
25.3.10
674/995
Figure 250. USART data clock timing diagram (M=1)
Figure 251. RX data setup/hold time
The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter
for more details.
Single-wire half-duplex communication
The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
●
●
The USART can be configured to follow a single-wire half-duplex protocol. In single-wire
half-duplex mode, the TX and RX pins are connected internally. The selection between half-
and full-duplex communication is made with a control bit ‘HALF DUPLEX SEL’ (HDSEL in
USART_CR3).
As soon as HDSEL is written to 1:
●
●
LINEN and CLKEN bits in the USART_CR2 register,
SCEN and IREN bits in the USART_CR3 register.
RX is no longer used,
TX is always released when no data is transmitted. Thus, it acts as a standard I/O in
idle or in reception. It means that the I/O must be configured so that TX is configured as
floating input (or output high open-drain) when not driven by the USART.
t
SCLK (capture strobe on SCLK
rising edge in this example)
SETUP
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
=
t
HOLD
Capture Strobe
Data on RX
(from slave)
Data on TX
(from master)
1/16 bit time
Idle or preceding
transmission
Data on RX
(from slave)
Start
Start
Doc ID 13902 Rev 9
LSB
LSB
0
0
1
1
M=1 (9 data bits)
2
2
t
SETUP
3
3
valid DATA bit
4
4
5
5
t
HOLD
* LBCL bit controls last data clock pulse
6
6
7
7
MSB
*
MSB Stop
*
8
8
*
*
*
Stop
Idle or next
transmission
RM0008