MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 331

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
14.3.3
Figure 118. Counter timing diagram, Update event with ARPE=1 (counter overflow)
Clock selection
The counter clock can be provided by the following clock sources:
●
●
●
●
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 119
without prescaler.
Internal clock (CK_INT)
External clock mode1: external input pin (TIx)
External clock mode2: external trigger input (ETR)
Internal trigger inputs (ITRx) : using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to
one timer as prescaler for the another on page 350
shows the behavior of the control circuit and the upcounter in normal mode,
Auto-reload preload register
Auto-reload active register
Update interrupt flag (UIF)
Timer clock = CK_CNT
Update event (UEV)
Counter overflow
Counter register
Write a new value in TIMx_ARR
Doc ID 13902 Rev 9
CNT_EN
CK_INT
FD
FD
F7
F8 F9 FA FB FC
for more details.
36
General-purpose timer (TIMx)
35 34 33 32 31 30 2F
36
36
: Using
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