MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 917

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
1
15
14
Bits 15:10 Reserved
Bits 2:0 Reserved
Bits 8:4 Reserved
Bits 2:0 Reserved
Ethernet MAC interrupt mask register (ETH_MACIMR)
Address offset: 0x003C
Reset value: 0x0000 0000
The ETH_MACIMR register bits make it possible to mask the interrupt signal due to the
corresponding event in the ETH_MACSR register.
Ethernet MAC address 0 high register (ETH_MACA0HR)
Address offset: 0x0040
Reset value: 0x0010 FFFF
The MAC address 0 high register holds the upper 16 bits of the 6-byte first MAC address of
the station. Note that the first DA byte that is received on the MII interface corresponds to
the LS Byte (bits [7:0]) of the MAC address low register. For example, if 0x1122 3344 5566
is received (0x11 is the first byte) on the MII as the destination address, then the MAC
address 0 register [47:0] is compared with 0x6655 4433 2211.
Bit 4 MMCS: MMC status
Bit 3 PMTS: PMT status
Bit 9 TSTIM: Time stamp trigger interrupt mask
Bit 3 PMTIM: PMT interrupt mask
13
Reserved
This bit is set high whenever any of bits 6:5 is set high. It is cleared only when both bits are low.
This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power-down
mode (See bits 5 and 6 in the ETH_MACPMTCSR register
status register (ETH_MACPMTCSR) on page
this last register, are cleared due to a read operation to the ETH_MACPMTCSR register.
When set, this bit disables the time stamp interrupt generation.
When set, this bit disables the assertion of the interrupt signal due to the setting of the PMT
Status bit in ETH_MACSR.
12
Reserved
11
Ethernet (ETH): media access control (MAC) with DMA controller
10
TSTIM
rw
9
Doc ID 13902 Rev 9
8
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
7
Reserved
915). This bit is cleared when both bits[6:5], of
6
5
Ethernet MAC PMT control and
9
4
MACA0H
8
PMTIM
7
rw
3
6
5
2
4
Reserved
3
1
2
917/995
1
0
0