MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 925
MCBSTM32EXL
Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Specifications of MCBSTM32EXL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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RM0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 13:0 Reserved
Bits 31:0 TGFSCC: Transmitted good frames single collision counter
Bits 31:0 TGFMSCC: Transmitted good frames more single collision counter
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Ethernet MMC transmitted good frames after a single collision counter
register (ETH_MMCTGFSCCR)
Address offset: 0x014C
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after a single collision
in Half-duplex mode.
Ethernet MMC transmitted good frames after more than a single collision
counter register (ETH_MMCTGFMSCCR)
Address offset: 0x0150
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after more than a
single collision in Half-duplex mode.
Bit 15 TGFMSCM: Transmitted good frames more single collision mask
Bit 14 TGFSCM: Transmitted good frames single collision mask
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Setting this bit masks the interrupt when the transmitted good frames after more than a single
collision counter reaches half the maximum value.
Setting this bit masks the interrupt when the transmitted good frames after a single collision
counter reaches half the maximum value.
Transmitted good frames after a single collision counter.
Transmitted good frames after more than a single collision counter
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Ethernet (ETH): media access control (MAC) with DMA controller
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Doc ID 13902 Rev 9
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TGFMSCC
TGFSCC
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9
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925/995
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