MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 628

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inter-integrated circuit (I
628/995
Header matched (10-bit mode only): the interface generates an acknowledge pulse if the
ACK bit is set and waits for the 8-bit slave address.
Address matched: the interface generates in sequence:
●
●
●
In 10-bit mode, after receiving the address sequence the slave is always in Receiver mode.
It will enter Transmitter mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
The TRA bit indicates whether the slave is in Receiver or Transmitter mode.
Slave transmitter
Following the address reception and after clearing ADDR, the slave sends bytes from the
DR register to the SDA line via the internal shift register.
The slave stretches SCL low until ADDR is cleared and DR filled with the data to be sent
(see
When the acknowledge pulse is received:
●
If TxE is set and some data were not written in the I2C_DR register before the end of the
next data transmission, the BTF bit is set and the interface waits until BTF is cleared by a
read to I2C_SR1 followed by a write to the I2C_DR register, stretching SCL low.
Figure 233. Transfer sequence diagram for slave transmitter
An acknowledge pulse if the ACK bit is set
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is
set.
If ENDUAL=1, the software has to read the DUALF bit to check which slave address
has been acknowledged.
The TxE bit is set by hardware with an interrupt if the ITEVFEN and the ITBUFEN bits
are set.
Figure 233
2
C) interface
Transfer sequencing EV1 EV3).
Doc ID 13902 Rev 9
RM0008