MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 879

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
27.6.1
27.6.2
Figure 310. Descriptor ring and chain structure
Initialization of a transfer using DMA
Initialization for the MAC is as follows:
1.
2.
3.
4.
5.
6.
7.
Host bus burst access
The DMA attempts to execute fixed-length burst transfers on the AHB master interface if
configured to do so (FB bit in ETH_DMABMR). The maximum burst length is indicated and
limited by the PBL field (ETH_DMABMR [13:8]). The receive and transmit descriptors are
always accessed in the maximum possible burst size (limited by PBL) for the 16 bytes to be
read.
The Transmit DMA initiates a data transfer only when there is sufficient space in the
Transmit FIFO to accommodate the configured burst or the number of bytes until the end of
frame (when it is less than the configured burst length). The DMA indicates the start address
and the number of transfers required to the AHB Master Interface. When the AHB Interface
is configured for fixed-length burst, then it transfers data using the best combination of
Write to ETH_DMABMR to set STM32F107xx bus access parameters.
Write to the ETH_DMAIER register to mask unnecessary interrupt causes.
The software driver creates the transmit and receive descriptor lists. Then it writes to
both the ETH_DMARDLAR and ETH_DMATDLAR registers, providing the DMA with
the start address of each list.
Write to MAC Registers 1, 2, and 3 to choose the desired filtering options.
Write to the MAC ETH_MACCR register to configure and enable the transmit and
receive operating modes. The PS and DM bits are set based on the auto-negotiation
result (read from the PHY).
Write to the ETH_DMAOMR register to set bits 13 and 1 and start transmission and
reception.
The transmit and receive engines enter the running state and attempt to acquire
descriptors from the respective descriptor lists. The receive and transmit engines then
begin processing receive and transmit operations. The transmit and receive processes
are independent of each other and can be started or stopped separately.
Descriptor 0
Descriptor 2
Descriptor 1
Descriptor n
Ethernet (ETH): media access control (MAC) with DMA controller
Ring structure
Doc ID 13902 Rev 9
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Next descriptor
Descriptor 0
Descriptor 1
Descriptor 2
Chain structure
Buffer 1
Buffer 1
Buffer 1
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