MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 627

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
24.3.2
Note:
Figure 232. I
I
By default the I
Master mode a Start condition generation is needed.
The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
●
●
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0),
where xx denotes the two most significant bits of the address.
Header or address not matched: the interface ignores it and waits for another Start
condition.
2
C slave mode
SMBALERT
Note: SMBALERT is an optional signal in SMBus mode. This signal is not applicable if
2 MHz in Standard mode
4 MHz in Fast mode
SDA
SCL
SMBus is disabled.
2
C block diagram
2
C interface operates in Slave mode. To switch from default Slave mode to
CLOCK CONTROL
CONTROL REGISTERS
STATUS REGISTERS
REGISTER (CCR)
CONTROL
CONTROL
CLOCK
DATA
(SR1&SR2)
(CR1&CR2)
Doc ID 13902 Rev 9
DUAL ADDRESS REGISTER
OWN ADDRESS REGISTER
INTERRUPTS
COMPARATOR
DATA SHIFT REGISTER
PEC REGISTER
DATA REGISTER
Inter-integrated circuit (I
CONTROL
LOGIC
DMA REQUESTS & ACK
PEC CALCULATION
2
C) interface
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