MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 572

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Controller area network (bxCAN)
22.9.3
572/995
Bits 25:24 SJW[1:0]
Bits 22:20 TS2[2:0]
Bits 19:16 TS1[3:0]
Bits 15:10
Bits 9:0 BRP[9:0]
Bit 23
CAN mailbox registers
This chapter describes the registers of the transmit and receive mailboxes. Refer to
Section 22.7.5: Message storage on page 556
Transmit and receive mailboxes have the same registers except:
●
●
●
There are 3 TX Mailboxes and 2 RX Mailboxes. Each RX Mailbox allows access to a 3 level
depth FIFO, the access being offered only to the oldest received message in the FIFO.
Each mailbox consist of 4 registers.
CAN_RI0R
CAN_RDT0R
CAN_RL0R
CAN_RH0R
The FMI field in the CAN_RDTxR register.
A receive mailbox is always write protected.
A transmit mailbox is write-enabled only while empty, corresponding TME bit in the
CAN_TSR register set.
FIFO0
These bits define the maximum number of time quanta the CAN hardware is allowed to
lengthen or shorten a bit to perform the resynchronization.
t
Reserved, forced by hardware to 0.
These bits define the number of time quanta in Time Segment 2.
t
These bits define the number of time quanta in Time Segment 1
t
For more information on bit timing, please refer to
Reserved, forced by hardware to 0.
These bits define the length of a time quanta.
t
RJW
BS2
BS1
q
= (BRP[9:0]+1) x t
= t
= t
= t
:
CAN
CAN
:
:
:
CAN
Time segment 2
Time segment 1
Baud rate prescaler
Resynchronization jump width
x (TS2[2:0] + 1)
x (TS1[3:0] + 1)
x (SJW[1:0] + 1)
CAN_RI1R
CAN_RDT1R
CAN_RL1R
CAN_RH1R
FIFO1
PCLK
Doc ID 13902 Rev 9
CAN_TI0R
CAN_TDT0R
CAN_TDL0R
CAN_TDH0R
for detailed register mapping.
Section 22.7.7: Bit timing on page
Three Tx Mailboxes
CAN_TI1R
CAN_TDT1R
CAN_TDL1R
CAN_TDH1R
CAN_TI2R
CAN_TDT2R
CAN_TDL2R
CAN_TDH2R
RM0008
558.