MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 898

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
898/995
31 30 29 28 27 26 25
Bits 29:16 FL: Frame length
Bit 31 OWN: Own bit
Bit 30 AFM: Destination address filter fail
Rx DMA descriptors
The descriptor structure consists of four 32-bit words (16 bytes). These are shown in
Figure
Figure 316. Rx DMA descriptor structure
●
RDES0: Receive descriptor Word0
RDES0 contains the received frame status, the frame length and the descriptor
ownership information.
When set, this bit indicates that the descriptor is owned by the DMA of the MAC Subsystem.
When this bit is reset, it indicates that the descriptor is owned by the Host. The DMA clears this bit
either when it completes the frame reception or when the buffers that are associated with this
descriptor are full.
When set, this bit indicates a frame that failed the DA filter in the MAC Core.
These bits indicate the byte length of the received frame that was transferred to host memory
(including CRC). This field is valid only when last descriptor (RDES0[8]) is set and descriptor error
(RDES0[14]) is reset.
This field is valid when last descriptor (RDES0[8]) is set. When the last descriptor and error
summary bits are not set, this field indicates the accumulated number of bytes that have been
transferred for the current frame.
316. The bit descriptions of RDES0, RDES1, RDES2 and RDES3 are given below.
RDES 0
RDES 1
RDES 2
RDES 3
24
CT
RL
31
O
W
N
23 22 21 20 19 18 17 16 15 14 13 12 11 10
FL
Reserved
[30:29]
Buffer 2 address [31:0] or Next descriptor address [31:0]
Buffer 2 byte count
Doc ID 13902 Rev 9
[28:16]
rw
Buffer 1 address [31:0]
Status [30:0]
[15:14]
CTRL
Res.
9
Buffer 1 byte count
8
7
[12:0]
6
5
4
3
ai15644
0
2
RM0008
1
0