MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 891

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bits 31:0 TBAP2 / TTSH: Transmit buffer 2 address pointer (Next descriptor address) / Transmit frame
Tx DMA descriptor format with IEEE1588 time stamp
The descriptor format (as described previously) and field descriptions remain unchanged
when created by software (OWN bit is set in TDES0). However, if the software has enabled
the IEEE 1588 functionality, the TDES2 and TDES3 descriptor fields take on a different
meaning when the DMA closes the descriptor (OWN bit in TDES0 is cleared).
The Transmit descriptor has additional control and status bits (TTSE and TTSS,
respectively) for time stamping, as shown in
(when the OWN bit is set), instructing the core to generate a time stamp for the
corresponding Ethernet frame being transmitted. The DMA sets the TTSS bit if the time
stamp has been updated in the TDES2 and TDES3 fields when the descriptor is closed
(OWN bit is cleared).
Figure 314. Transmit descriptor field format with IEEE1588 time stamp enabled
1. The DMA updates TDES2 and TDES3 with the time stamp value before clearing the OWN bit in TDES0:
TDES2 is updated with the lower 32 time stamp bits (the sub-second field, called TTSL in subsequent
section
Seconds field, called TTSH in subsequent sections
time stamp high
These bits take on two different functions: the application uses them to indicate to the DMA the
location of data in memory. And then after transferring all these data, the DMA may then use
these bits to pass back time stamp data.
TBAP2: When the software makes this descriptor available to the DMA (at the moment when
the OWN bit is set to 1 in TDES0), these bits indicate the physical address of Buffer 2 when a
descriptor ring structure is used. If the Second address chained (TDES1 [24]) bit is set, this
address contains the pointer to the physical memory where the next descriptor is present. The buffer
address pointer must be aligned to the bus width only when TDES1 [24] is set. (LSBs are ignored
internally.)
TTSH: Before it clears the OWN bit in TDES0, the DMA updates this field with the 32 most
significant bits of the time stamp captured for the corresponding transmit frame (overwriting the
value for TBAP2). This field has the time stamp only if time stamping is activated for this frame
(see TDES0 bit 25, TTSE) and if the Last segment control bit (LS) in the descriptor is set.
TDES 0
TDES 1
TDES 2
TDES 3
TDES2: Transmit descriptor
31
O
W
N
Reserved
Buffer 2 address [31:0] or Next descriptor address [31:0] / Time stamp high [31:0]
[31:29]
[30:26]
Ctrl
Ethernet (ETH): media access control (MAC) with DMA controller
S
E
T
T
Buffer 2 byte count
Res.
Doc ID 13902 Rev 9
Buffer 1 address [31:0] / Time stamp low [31:0]
24
Word2) and TDES3 is updated with the upper 32 time stamp bits (the
[28:16]
[23:20]
Ctrl
Reserved
Figure 314.
[19:18]
TDES3: Transmit descriptor
Reserved
[15:13]
S
S
T
T
The software sets the TTSE bit
Status [16:0]
Buffer 1 byte count
(1)
Word3)
[12:0]
(1)
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