MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 526

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal serial bus full-speed device interface (USB)
Note:
21.5
21.5.1
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CTRM PMAOVRM ERRM WKUPM SUSPM RESETM SOFM ESOFM
15
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14
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A device may require to exit from suspend mode as an answer to particular events not
directly related to the USB protocol (e.g. a mouse movement wakes up the whole system).
In this case, the resume sequence can be started by setting the RESUME bit in the
USB_CNTR register to ‘1’ and resetting it to 0 after an interval between 1mS and 15mS (this
interval can be timed using ESOF interrupts, occurring with a 1mS period when the system
clock is running at nominal frequency). Once the RESUME bit is clear, the resume
sequence will be completed by the host PC and its end can be monitored again using the
RXDP and RXDM bits in the USB_FNR register.
The RESUME bit must be anyway used only after the USB peripheral has been put in
suspend mode, setting the FSUSP bit in USB_CNTR register to 1.
USB registers
The USB peripheral registers can be divided into the following groups:
●
●
●
All register addresses are expressed as offsets with respect to the USB peripheral registers
base address 0x4000 5C00, except the buffer descriptor table locations, which starts at the
address specified by the USB_BTABLE register. Due to the common limitation of APB1
bridges on word addressability, all register addresses are aligned to 32-bit word boundaries
although they are 16-bit wide. The same address alignment is used to access packet buffer
memory locations, which are located starting from 0x4000 6000.
Refer to
Common registers
These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.
USB control register (USB_CNTR)
Address offset: 0x40
Reset value: 0x0003
Bit 15 CTRM: Correct transfer interrupt mask
Bit 14 PMAOVRM: Packet memory area over / underrun interrupt mask
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Common Registers: Interrupt and Control registers
Endpoint Registers: Endpoint configuration and status
Buffer Descriptor Table: Location of packet memory used to locate data buffers
Section 1.1 on page 37
0: Correct Transfer (CTR) Interrupt disabled.
1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
0: PMAOVR Interrupt disabled.
1: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit
in the USB_ISTR register is set.
12
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11
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10
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9
Doc ID 13902 Rev 9
for a list of abbreviations used in register descriptions.
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8
7
Reserved
Res.
6
5
RESUME FSUSP LP_MODE PDWN FRES
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4
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3
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2
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1
RM0008
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0