MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 984

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision history
984/995
Table 215. Document revision history (continued)
22-May-2008
08-Feb-2008
Date
continued
Revision
on next
page
3
4
Figure 4: Power supply overview on page 53
Section 6.1.2: Power reset on page 75
Section 6.2: Clocks on page 76
Definition of Bits 26:24 modified in
configuration register (AFIO_MAPR) on page
AFIO_EVCR
page
Number of maskable interrupt channels modified in
vectored interrupt controller (NVIC) on page 169
Section 10.3.6: Interrupts on page 187
Examples modified in
(OSSR=1) on page
Table 73: Output control bits for complementary OCx and OCxN channels
with break feature on page 310
Register names modified in
page
Small text change in
Bits 5:0 frequency description modified in
(I2C_CR2) on page
Section 21.3.1: Description of USB blocks on page 514
Section 23.3.4: Simplex communication on page 594
Section 23.3.6: CRC calculation on page 595
Note added in
Section 23.3.9: Disabling the SPI on page 598
Appendix A: Important notes, removed.
Reference manual updated to apply to devices containing up to 512 Kbytes
of Flash memory (High-density devices). Document restructured. Small text
changes. Definitions of Medium-density and High-density devices added to
all sections.
In
–
– Note and text added to
– SRAM size in
–
– Prefetch buffer on/off specified in
bit_number definition modified in
Section 3: CRC calculation unit on page 50
boundary addresses on page 41
page 39
clock enable register (RCC_AHBENR) on page
Entering Stop mode on page 59
Updated in
backup registers and available storage size and
introduction. ASOE definition modified in
calibration register (BKP_RTCCR) on page
Figure 1: System architecture on page
page
Section 2.3.3: Embedded Flash memory on page 44
page size, number of pages,
module organization (high-density devices) on page 46
Section 2: Memory and bus architecture on page
167.
579.
39,
updated and CRCEN bit added to
Doc ID 13902 Rev 9
bits corrected in
Table 1: Register boundary addresses on page 41
Section 5: Backup registers (BKP) on page
BUSY flag on page
Section 2.3.1: Embedded SRAM on page 42
283.
643.
Section 24.3.3: I2C master mode on page
Figure 90: 6-step generation, COM example
AHB/APB bridges (APB) on page 40
Table 51: AFIO register map and reset values on
Section 22.9.4: CAN filter registers on
Reading the Flash
modified.
modified.
specified.
updated,
Changes
Section 2.3.2: Bit banding on page
595.
Section 8.4.2: AF remap and debug I/O
Reading the Flash memory
modified.
added. Small text changes.
38,
Section 5.4.2: RTC clock
Section 24.6.2: Control register 2
Figure 2: Memory map on
Section 6.3.6: AHB peripheral
added
68.
Figure 2: Memory map on
modified.
159.
modified.
added.
93).
.
Section 5.1: BKP
memory,
(Table 1: Register
Section 9.1: Nested
38:
modified.
updated (Flash size,
66: number of
modified.
added)
Table 4: Flash
updated
630.
RM0008
43.