MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 159

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
8.4.2
REMAP
PD01_
31
15
rw
CAN_REMAP
30
14
rw
Bits 31:27
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration
Bits 23:21
Bits 6:4 PORT[2:0]: Port selection
Bits 3:0 PIN[3:0]: Pin selection (x = A .. E)
[1:0]
AF remap and debug I/O configuration register (AFIO_MAPR)
Address offset: 0x04
Reset value: 0x0000 0000
Memory map and bit definitions for low-, medium- and high-density devices:
Reserved
29
13
rw
Note: The EVENTOUT signal output capability is not extended to ports PF and PG.
REMAP
TIM4_
Set and cleared by software. Select the port used to output the Cortex EVENTOUT signal.
000: PA selected
001: PB selected
010: PC selected
011: PD selected
100: PE selected
Set and cleared by software. Select the pin used to output the Cortex EVENTOUT signal.
0000: Px0 selected
0001: Px1 selected
0010: Px2 selected
0011: Px3 selected
...
1111: Px15 selected
Reserved
These bits are write-only (when read, the value is undefined). They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD
access to the Cortex debug port. The default state after reset is SWJ ON without trace. This
allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /
JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
Reserved
28
12
rw
TIM3_REMAP
27
11
rw
[1:0]
26
10
rw
w
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
CFG[2:0]
SWJ_
TIM2_REMAP
25
rw
w
9
Doc ID 13902 Rev 9
[1:0]
24
rw
w
8
TIM1_REMAP
23
rw
7
[1:0]
Reserved
22
rw
6
REMAP[1:0]
21
rw
5
USART3_
ETRGR
EG_RE
ADC2_
MAP
20
rw
rw
4
ETRGIN
REMAP
J_REM
USART
ADC2_
AP
19
rw
2_
rw
3
ETRGR
REMAP
EG_RE
USART
ADC1_
MAP
18
1_
rw
rw
2
ETRGIN
REMAP
ADC1_
J_REM
I2C1_
AP
17
rw
rw
1
159/995
TIM5CH
4_IREM
REMAP
SPI1_
AP
16
rw
rw
0