MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 380

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Basic timers (TIM6&TIM7)
15.3.3
380/995
Figure 152. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
Figure 153. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 154
without prescaler.
shows the behavior of the control circuit and the upcounter in normal mode,
preloaded)
preloaded)
Auto-reload shadow register
Auto-reload preload register
Update interrupt flag (UIF)
Update interrupt flag (UIF)
Timer clock = CK_CNT
Timer clock = CK_CNT
Auto-reload register
Update event (UEV)
Update event (UEV)
Counter overflow
Counter overflow
Counter register
Counter register
Write a new value in TIMx_ARR
Write a new value in TIMx_ARR
Doc ID 13902 Rev 9
CNT_EN
CK_PSC
CNT_EN
CK_INT
FF
F5
F5
31
F0
32 33 34 35 36
F1 F2 F3 F4 F5
00
00
01 02 03 04 05 06 07
01 02 03 04 05 06 07
36
36
36
RM0008

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