MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 909

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
RA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw
Bits 30:11 Reserved
Bits 7:6 PCF: Pass control frames
Ethernet MAC frame filter register (ETH_MACFFR)
Address offset: 0x0004
Reset value: 0x0000 0000
The MAC frame filter register contains the filter controls for receiving frames. Some of the
controls from this register go to the address check block of the MAC, which performs the first
level of address filtering. The second level of filtering is performed on the incoming frame,
based on other controls such as pass bad frames and pass control frames.
Bit 31 RA: Receive all
Bit 10 HPF: Hash or perfect filter
Bit 9 SAF: Source address filter
Bit 8 SAIF: Source address inverse filtering
Bit 5 BFD: Broadcast frames disable
Bit 4 PAM: Pass all multicast
When this bit is set, the MAC receiver passes all received frames on to the application,
irrespective of whether they have passed the address filter. The result of the SA/DA filtering is
updated (pass or fail) in the corresponding bits in the receive status word. When this bit is
reset, the MAC receiver passes on to the application only those frames that have passed the
SA/DA address filter.
When set, this bit configures the address filter to pass a frame if it matches either the perfect
filtering or the hash filtering as set by the HM or HU bit. When low and if the HU/HM bit is set,
the frame is passed only if it matches the Hash filter.
The MAC core compares the SA field of the received frames with the values programmed in
the enabled SA registers. If the comparison matches, then the SAMatch bit in the RxStatus
word is set high. When this bit is set high and the SA filter fails, the MAC drops the frame.
When this bit is reset, the MAC core forwards the received frame to the application. It also
forwards the updated SA Match bit in RxStatus depending on the SA address comparison.
When this bit is set, the address check block operates in inverse filtering mode for the SA
address comparison. The frames whose SA matches the SA registers are marked as failing
the SA address filter.
When this bit is reset, frames whose SA does not match the SA registers are marked as failing
the SA address filter.
These bits control the forwarding of all control frames (including unicast and multicast PAUSE
frames). Note that the processing of PAUSE control frames depends only on RFCE in Flow
Control Register[2].
When this bit is set, the address filters filter all incoming broadcast frames.
When this bit is reset, the address filters pass all received broadcast frames.
When set, this bit indicates that all received frames with a multicast destination address (first
bit in the destination address field is '1') are passed.
When reset, filtering of multicast frame depends on the HM bit.
00 or 01: MAC prevents all control frames from reaching the application
10: MAC forwards all control frames to application even if they fail the address filter
11: MAC forwards control frames that pass the address filter.
Reserved
Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 9
rw rw rw rw rw rw rw rw rw rw rw
9
8
7
6
5
4
3
2
909/995
1
0