MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 689

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Note:
Bits 3:0 ADD[3:0]: Address of the USART node
These 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.
Bit 11 CLKEN: Clock enable
Bit 10 CPOL: Clock polarity
Bit 9 CPHA: Clock phase
Bit 8 LBCL: Last bit clock pulse
Bit 7 Reserved, forced by hardware to 0.
Bit 6 LBDIE: LIN break detection interrupt enable
Bit 5 LBDL: lin break detection length
Bit 4 Reserved, forced by hardware to 0.
Note: This bit is not available for UART4 & UART5.
Note: This bit is not available for UART4 & UART5.
Note: This bit is not available for UART4 & UART5.
Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format
This bit allows the user to enable the SCLK pin.
0: SCLK pin disabled
1: SCLK pin enabled
This bit allows the user to select the polarity of the clock output on the SCLK pin in
synchronous mode. It works in conjunction with the CPHA bit to produce the desired
clock/data relationship
0: Steady low value on SCLK pin outside transmission window.
1: Steady high value on SCLK pin outside transmission window.
This bit allows the user to select the phase of the clock output on the SCLK pin in
synchronous mode. It works in conjunction with the CPOL bit to produce the desired
clock/data relationship (see figures
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first data capture edge.
This bit allows the user to select whether the clock pulse associated with the last data bit
transmitted (MSB) has to be output on the SCLK pin in synchronous mode.
0: The clock pulse of the last data bit is not output to the SCLK pin
1: The clock pulse of the last data bit is output to the SCLK pin
Break interrupt mask (break detection using break delimiter).
0: Interrupt is inhibited
1: An interrupt is generated whenever LBD=1 in the USART_SR register
This bit is for selection between 11 bit or 10 bit break detection.
0: 10 bit break detection
1: 11 bit break detection
This bit-field gives the address of the USART node.
This is used in multiprocessor communication during mute mode, for wake up with address
mark detection.
selected by the M bit in the USART_CR1 register.
2: This bit is not available for UART4 & UART5.
Universal synchronous asynchronous receiver transmitter (USART)
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