MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 401

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
17.4
17.4.1
17.4.2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, read as 0.
Bits 15:0 KEY[15:0]: Key value (write only, read 0000h)
Bits 31:3 Reserved, read as 0.
Bits 2:0 PR[2:0]: Prescaler divider
The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy.
For more details refer to
IWDG registers
Refer to
Key register (IWDG_KR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
Prescaler register (IWDG_PR)
Address offset: 0x04
Reset value: 0x0000 0000
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
9
These bits must be written by software at regular intervals with the key value AAAAh,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 5555h to enables access to the IWDG_PR and IWDG_RLR registers
(see
Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is
selected)
These bits are write access protected
select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in
order to be able to change the prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Section 1.1 on page 37
Reserved
Reserved
8
Section
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG_SR
register is reset.
7
6
17.3.2)
5
4
LSI calibration on page
3
Doc ID 13902 Rev 9
2
for a list of abbreviations used in register descriptions.
1
0
w
seeSection
w
w
80.
w
w
17.3.2. They are written by software to
w
Reserved
Independent watchdog (IWDG)
9
w
9
KEY[15:0]
8
w
8
7
w
7
6
w
6
5
w
5
4
w
4
3
w
3
rw rw rw
2
w
2
PR[2:0]
401/995
1
w
1
0
w
0