MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 632

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inter-integrated circuit (I
Note:
Figure 235. Transfer sequence diagram for master transmitter
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Closing the communication
After writing the last byte to the DR register, the STOP bit is set by software to generate a
Stop condition (see
automatically back to slave mode (M/SL bit cleared).
Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.
Master receiver
Following the address transmission and after clearing ADDR, the I
Master Receiver mode. In this mode the interface receives bytes from the SDA line into the
DR register via the internal shift register. After each byte the interface generates in
sequence:
●
●
If the RxNE bit is set and the data in the DR register is not read before the end of the last
data reception, the BTF bit is set by hardware and the interface waits until BTF is cleared by
a read in the SR1 register followed by a read in the DR register, stretching SCL low.
An acknowledge pulse if the ACK bit is set
The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are
set (see
2
Figure 236
C) interface
Figure 235
Transfer sequencing EV7).
Doc ID 13902 Rev 9
Transfer sequencing EV8_2). The interface goes
2
C interface enters
RM0008