MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 262

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced-control timers (TIM1&TIM8)
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Figure 63. Counter timing diagram, internal clock divided by N
Figure 64. Counter timing diagram, update event when repetition counter is not
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
used
Update interrupt flag (UIF)
Update interrupt flag (UIF)
Timer clock = CK_CNT
Timer clock = CK_CNT
Auto-reload register
Update event (UEV)
Update event (UEV)
Counter underflow
Counter underflow
Counter register
Counter register
Write a new value in TIMx_ARR
Doc ID 13902 Rev 9
CK_PSC
CK_PSC
CEN
FF
20
05
04 03 02 01 00
1F
36
00
35 34 33 32 31 30 2F
36
36
RM0008