MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 645

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
24.6.4
24.6.5
15
15
14
14
Bits 15:8 Reserved, forced by hardware to 0.
Bits 15:8 Reserved, forced by hardware to 0.
Bits 7:1 ADD2[7:1]: Interface address
Bits 7:0 DR[7:0] 8-bit data register
Own address register 2 (I2C_OAR2)
Address offset: 0x0C
Reset value: 0x0000
Data register (I2C_DR)
Address offset: 0x10
Reset value: 0x0000
Bit 0 ENDUAL: Dual addressing mode enable
13
13
Note: In slave mode, the address is not copied into DR.
Note: Write collision is not managed (DR can be written if TxE=0).
Note: If an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so
12
bits 7:1 of address in dual addressing mode
0: Only OAR1 is recognized in 7-bit addressing mode
1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode
12
Reserved
Reserved
Byte received or to be transmitted to the bus.
–Transmitter mode: Byte transmission starts automatically when a byte is written in the DR
–Receiver mode: Received byte is copied into DR (RxNE=1). A continuous transmit stream
register. A continuous transmit stream can be maintained if the next data to be
transmitted is put in DR once the transmission is started (TxE=1)
can be maintained if DR is read before the next data byte is received (RxNE=1).
cannot be read.
11
11
10
10
9
9
Doc ID 13902 Rev 9
8
8
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7
7
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6
6
Inter-integrated circuit (I
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5
5
ADD2[7:1]
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4
4
DR[7:0]
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3
3
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rw
2
2
2
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C) interface
1
1
ENDUAL
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0
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