MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 445

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Figure 175. NAND/PC Card controller timing for common memory access
1. NOE remains high (inactive) during write access. NWE remains high (inactive) during read access.
2. NCEx goes low as soon as NAND access is requested and remains low until a different memory bank is accessed.
19.6.4
write_data
read_data
NCEx
A[25:0]
NREG,
NIOW,
NIOR
NWE,
NOE
HCLK
(1)
(2)
High
NAND Flash operations
The command latch enable (CLE) and address latch enable (ALE) signals of the NAND
Flash device are driven by some address signals of the FSMC controller. This means that to
send a command or an address to the NAND Flash memory, the CPU has to perform a write
to a certain address in its memory space.
A typical page read operation from the NAND Flash device is as follows:
1.
2.
3.
Program and enable the corresponding memory bank by configuring the FSMC_PCRx
and FSMC_PMEMx (and for some devices, FSMC_PATTx, see
Flash pre-wait functionality on page
the NAND Flash (PWID bits for the databus width of the NAND Flash, PTYP = 1,
PWAITEN = 1, PBKEN = 1, see section
(FSMC_PMEM2..4) on page 450
The CPU performs a byte write in the common memory space, with data byte equal to
one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The
CLE input of the NAND Flash is active during the write strobe (low pulse on NWE), thus
the written byte is interpreted as a command by the NAND Flash. Once the command
is latched by the NAND Flash device, it does not need to be written for the following
page read operations.
The CPU can send the start address (STARTAD) for a read operation by writing four
bytes (or three for smaller capacity devices), STARTAD[7:0], then STARTAD[16:9],
STARTAD[24:17] and finally STARTAD[25] for 64 Mb x 8 bit NAND Flash) in the
common memory or attribute space. The ALE input of the NAND Flash device is active
during the write strobe (low pulse on NWE), thus the written bytes are interpreted as
MEMxSET + 1
MEMxHIZ + 1
Doc ID 13902 Rev 9
for timing configuration).
MEMxWAIT + 1
446) registers according to the characteristics of
Common memory space timing register 2..4
Flexible static memory controller (FSMC)
Valid
MEMxHOLD + 1
Section 19.6.5: NAND
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