MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 813

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
5.
6.
Figure 276
Figure 276. Receive FIFO packet read in slave mode
●
This section describes how the core handles SETUP packets and the application’s
sequence for handling SETUP transactions.
c)
d)
e)
After the data payload is popped from the receive FIFO, the RXFLVL interrupt
(OTG_FS_GINTSTS) must be unmasked.
Steps 1–5 are repeated every time the application detects assertion of the interrupt line
due to RXFLVL in OTG_FS_GINTSTS. Reading an empty receive FIFO can result in
undefined core behavior.
SETUP transactions
Setup stage done pattern:
PKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num,
DPID = Don’t Care (0b00).
These data indicate that the Setup stage for the specified endpoint has completed
and the Data stage has started. After this entry is popped from the receive FIFO,
the core asserts a Setup interrupt on the specified control OUT endpoint.
Data OUT packet pattern:
PKTSTS = DataOUT, BCNT = size of the received data OUT packet (0  BCNT
 1 024), EPNUM = EPNUM on which the packet was received, DPID = Actual
Data PID.
Data transfer completed pattern:
PKTSTS = Data OUT Transfer Done, BCNT = 0x0, EPNUM = OUT EP Num
on which the data transfer is complete, DPID = Don’t Care (0b00).
These data indicate that an OUT data transfer for the specified OUT endpoint has
completed. After this entry is popped from the receive FIFO, the core asserts a
Transfer Completed interrupt on the specified OUT endpoint.
provides a flowchart of the above procedure.
memory
store in
packet
wait until RXFLVL in OTG_FS_GINTSTSG
rd_data = rd_reg (OTG_FS_GRXSTSP);
Y
rd_rxfifo(rd_data.EPNUM,
Doc ID 13902 Rev 9
mem[0:dword_cnt-1] =
rd_data.BCNT = 0
dword_cnt )
N
USB on-the-go full-speed (OTG_FS)
(BCNT[1] | BCNT[1])
dword_cnt =
BCNT[11:2] +
C
rcv_out_pkt ()
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