MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 991

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Table 215. Document revision history (continued)
22-Jun-2009
Date
Revision
9
Reference manual updated to support also STM32F105xx/STM32F107xx
connectivity line devices.
Memory and bus architecture
Section 3.3: CRC functional description
Note modified in
Connectivity line devices: reset and clock control (RCC)
Reset circuit
description in
SPI3 remapping
DMA section:
bits PINC = MINC = 1)
Pointer incrementation on page 184
address register (DMA_CPARx) (x = 1 ..7)
address register (DMA_CMARx) (x = 1 ..7)
channel is enabled.
Advanced-control timer section:
on page 279
Section 13.4.18: TIM1&TIM8 break and dead-time register
CC1IF bit description modified in
(TIMx_SR)
Note added to
Internal trigger connection on page
Table 92: NOR Flash/PSRAM supported memories and transactions on
page 416
Register numbering and address offset corrected in
response 1..4 register (SDIO_RESPx) on page
In
access type modified, small text changes.
SPI section: note added in
pin management
master mode
Audio frequency precision tables
Clock generator on page 607
increased to 96 kHz.
Arbitration lost (ARLO) on page 634
USART section: Description of “1.5 stop bits” updated in
bits,
Section 25.3.2:
register values
clock deviation
Single-wire half-duplex communication
in
Debug support (DBG)
–
–
–
– in DBGMCU_IDCODE, REV_ID(15:0) updated for connectivity line
Section 26: USB on-the-go full-speed (OTG_FS)
changes.
Figure 320: Block diagram of STM32F10xxx-level and Cortex-M3-level
debug support
Section 29.15: ETM (Embedded Trace Macrocell)
Figure 323: TPIU block diagram
devices (revision Z added).
Section 25.6.4: Control register 1
Section 22: Controller area network
RTS flow control
Doc ID 13902 Rev 9
and
and
updated. PLL1 changed to PLL. Note added to BDP bit
updated. BKE and BKP bit descriptions updated in
and
Section 4.4.1: Power control register
Table 55: Programmable data width & endian behavior (when
Single-burst transfer
Table 72: TIMx Internal trigger connection
modified.
added.
Transmitter.
Section 14.4.5: TIMx status register
corrected.
Section 4.1.2: Battery backup
updated
clarified. Note added at the end of
Section 23.3.4: Simplex
corrected. Procedure sequence modified in
section:
Section 25.3.11: Smartcard
updated,
Section 25.3.5: USART receiver’s tolerance to
Section 23.2.2: I
How to derive USARTDIV from USART_BRR
and audio sampling frequency range
section:
Section 13.3.12: Using the break function
Section 10.3.1: DMA transactions
Section 13.4.5: TIM1&TIM8 status register
Changes
166
updated
modified.
359.
(USART_CR1).
modified.
specified.
and
Embedded boot loader
(bxCAN): DBF bit reset value and
updated. Bit 12 description modified
updated.
167
communication.
and
must not be written when the
2
S
DMA channel x peripheral
features.
added to
DMA channel x memory
domain.
500.
revised. Small text
(PWR_CR).
and
Section 20.9.6: SDIO
Section 23.3.3: SPI
(TIMx_SR).
added
Section 25.3.10:
Slave select (NSS)
Section 23.4.3:
section:
and
Configurable stop
Revision history
(TIMx_BDTR).
Table 76: TIMx
updated.
Table 48:
Figure 10:
and
991/995