MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 647

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bit 10 AF: Acknowledge failure
Bit 9 ARLO: Arbitration lost (master mode)
Bit 8 BERR: Bus error
Bit 7 TxE: Data register empty (transmitters)
Bit 6 RxNE: Data register not empty (receivers)
Bit 5 Reserved, forced by hardware to 0.
Bit 4 STOPF: Stop detection (slave mode)
Note: In SMBUS, the arbitration on the data in slave mode occurs only during the data
Note: TxE is not cleared by writing the first data being transmitted, or by writing data when
Note: RxNE is not cleared by reading data when BTF is set, as the data register is still full.
Note: The STOPF bit is not set after a NACK reception
0: No acknowledge failure
1: Acknowledge failure
–Set by hardware when no acknowledge is returned.
–Cleared by software writing 0, or by hardware when PE=0.
0: No Arbitration Lost detected
1: Arbitration Lost detected
Set by hardware when the interface loses the arbitration of the bus to another master
–Cleared by software writing 0, or by hardware when PE=0.
After an ARLO event the interface switches back automatically to Slave mode (M/SL=0).
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
–Set by hardware when the interface detects a misplaced Start or Stop condition
–Cleared by software writing 0, or by hardware when PE=0.
0: Data register not empty
1: Data register empty
–Set when DR is empty in transmission. TxE is not set during address phase.
–Cleared by software writing to the DR register or by hardware after a start or a stop
TxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)
0: Data register empty
1: Data register not empty
–Set when data register is not empty in receiver mode. RxNE is not set during address
–Cleared by software reading or writing the DR register or by hardware when PE=0.
RxNE is not set in case of ARLO event.
0: No Stop condition detected
1: Stop condition detected
–Set by hardware when a Stop condition is detected on the bus by the slave after an
–Cleared by software reading the SR1 register followed by a write in the CR1 register, or by
condition or when PE=0.
phase.
acknowledge (if ACK=1).
hardware when PE=0
phase, or the acknowledge transmission (not on the address acknowledge).
BTF is set, as in both cases the data register is still empty.
Doc ID 13902 Rev 9
Inter-integrated circuit (I
2
C) interface
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