MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 966

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug support (DBG)
29.10
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The address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes)
and consists of:
The AHB-AP of the Cortex-M3 includes 9 x 32-bits registers:
Table 206. Cortex-M3 AHB-AP registers
Refer to the Cortex-M3 r1p1 TRM for further details.
Core debug
Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the Advanced High-performance Bus (AHB-AP) port. The processor can
access these registers directly over the internal Private Peripheral Bus (PPB).
It consists of 4 registers:
Table 207. Core debug registers
Address
offset
0x0C
0x1C
0xFC
0xF8
Register
0x00
0x04
0x10
0x14
0x18
DEMCR
DHCSR
DCRSR
DCRDR
c)
d)
Bits [8:4] = the bits[7:4] APBANKSEL of the DP SELECT register
Bits [3:2] = the 2 address bits of A(3:2) of the 35-bit packet request for SW-DP.
AHB-AP Control and
Status Word
AHB-AP Transfer Address
AHB-AP Data Read/Write
AHB-AP Banked Data 0
AHB-AP Banked Data 1
AHB-AP Banked Data 2
AHB-AP Banked Data 3
AHB-AP Debug ROM Address Base Address of the debug interface
AHB-AP ID Register
The 32-bit Debug Halting Control and Status Register
This provides status information about the state of the processor enable core debug
halt and step the processor
The 17-bit Debug Core Register Selector Register:
This selects the processor register to transfer data to or from.
The 32-bit Debug Core Register Data Register:
This holds data for reading and writing registers to and from the processor selected
by the DCRSR (Selector) register.
The 32-bit Debug Exception and Monitor Control Register:
This provides Vector Catching and Debug Monitor Control. This register contains a
bit named TRCENA which enable the use of a TRACE.
Register name
Doc ID 13902 Rev 9
Configures and controls transfers through the AHB
interface (size, hprot, status on current transfer, address
increment type
Directly maps the 4 aligned data words without rewriting
the Transfer Address Register.
Description
Notes
RM0008