MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 357

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
14.4.3
ETP
15
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ECE
14
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Bits 6:4 MMS: Master mode selection
Bits 2:0 Reserved, always read as 0
TIMx slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
Bit 15 ETP: External trigger polarity
Bit 3 CCDS: Capture/compare DMA selection
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ETPS[1:0]
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and
the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO).
101: Compare - OC2REF signal is used as trigger output (TRGO).
110: Compare - OC3REF signal is used as trigger output (TRGO).
111: Compare - OC4REF signal is used as trigger output (TRGO).
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
12
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11
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10
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ETF[3:0]
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9
Doc ID 13902 Rev 9
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8
MSM
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7
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6
TS[2:0]
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5
General-purpose timer (TIMx)
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4
Res.
3
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2
SMS[2:0]
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1
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