MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 928

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:8 Reserved
Bits 7:0 STSSI: System time subsecond increment
Ethernet PTP subsecond increment register (ETH_PTPSSIR)
Address offset: 0x0704
Reset value: 0x0000 0000
This register contains the 8-bit value by which the subsecond register is incremented. In
Coarse update mode (TSFCU bit in ETH_PTPTSCR), the value in this register is added to
the system time every clock cycle of HCLK. In Fine update mode, the value in this register is
added to the system time whenever the accumulator gets an overflow.
Bit 2 TSSTI: Time stamp system time initialize
Bit 1 TSFCU: Time stamp fine or coarse update
Bit 0 TSE: Time stamp enable
When this bit is set, the system time is initialized (overwritten) with the value specified in the
Time stamp high update and Time stamp low update registers. This bit must be read as zero
before you can set it. When initialization is complete, this bit is cleared.
When set, this bit indicates that the system time stamp is to be updated using the Fine Update
method. When cleared, it indicates the system time stamp is to be updated using the Coarse
method.
When this bit is set, time stamping is enabled for transmit and receive frames. When this bit is
cleared, the time stamp function is suspended and time stamps are not added for transmit and
receive frames. Because the maintained system time is suspended, you must always initialize
the time stamp feature (system time) after setting this bit high.
The value programmed in this register is added to the contents of the subsecond value of the
system time in every update.
For example, to achieve 20 ns accuracy, the value is: 20 / 0.467 = ~ 43 (or 0x2A).
Reserved
Doc ID 13902 Rev 9
9
8
rw rw rw rw rw rw rw rw
7
6
5
STSSI
4
3
RM0008
2
1
0