MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 565

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
LOW2
ABRQ
31
15
rs
1
r
LOW1
30
14
r
CAN transmit status register (CAN_TSR)
Address offset: 0x08
Reset value: 0x1C00 0000
Bit 31 LOW2
Bit 30 LOW1
Bit 29 LOW0
Bit 28 TME2
Reserved
LOW0
Bit 2 ERRI
Bit 1 SLAK
Bit 0 INAK
Res.
29
13
r
Note: The LOW[2:0] bits are set to zero when only one mailbox is pending.
Note: The process of leaving Sleep mode is triggered when the SLEEP bit in the CAN_MCR
TME2
This bit is set by hardware when more than one mailbox are pending for transmission and
mailbox 2 has the lowest priority.
This bit is set by hardware when more than one mailbox are pending for transmission and
mailbox 1 has the lowest priority.
This bit is set by hardware when more than one mailbox are pending for transmission and
mailbox 0 has the lowest priority.
This bit is set by hardware when no transmit request is pending for mailbox 2.
This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and
the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status
change interrupt if the ERRIE bit in the CAN_IER register is set.
This bit is cleared by software.
This bit is set by hardware and indicates to the software that the CAN hardware is now in
Sleep mode. This bit acknowledges the Sleep mode request from the software (set SLEEP
bit in CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left Sleep mode (to be
synchronized on the CAN bus). To be synchronized the hardware has to monitor a
sequence of 11 consecutive recessive bits on the CAN RX signal.
This bit is set by hardware and indicates to the software that the CAN hardware is now in
initialization mode. This bit acknowledges the initialization request from the software (set
INRQ bit in CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left the initialization mode (to
be synchronized on the CAN bus). To be synchronized the hardware has to monitor a
sequence of 11 consecutive recessive bits on the CAN RX signal.
28
12
r
:
:
:
:
:
:
:
Error interrupt
Initialization acknowledge
Transmit mailbox 2 empty
register is cleared. Please refer to the AWUM bit of the CAN_MCR register description
for detailed information for clearing SLEEP bit
Lowest priority flag for mailbox 2
Lowest priority flag for mailbox 1
Lowest priority flag for mailbox 0
Sleep acknowledge
TME1
TERR
rc_w1
27
11
1
r
ALST1
TME0
rc_w1
26
10
r
TXOK
rc_w1
25
CODE[1:0]
9
1
r
Doc ID 13902 Rev 9
RQCP
rc_w1
24
8
1
r
ABRQ
ABRQ
23
rs
rs
2
7
0
22
6
Reserved
Reserved
21
5
Controller area network (bxCAN)
20
4
TERR
TERR
rc_w1
rc_w1
19
2
3
0
ALST2
ALST0
rc_w1
rc_w1
18
2
TXOK
rc_w1
TXOK
rc_w1
17
2
1
0
565/995
RQCP
RQCP
rc_w1
rc_w1
16
2
0
0