MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 436

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Flexible static memory controller (FSMC)
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit 19 CBURSTRW: Write burst enable.
Bit 15 Reserved.
Bit 14 EXTMOD: Extended mode enable.
Bit 13 WAITEN: Wait enable bit.
Bit 12 WREN: Write enable bit.
Bit 11 WAITCFG: Wait timing configuration.
NOR/PSRAM controller registers
SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4)
Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4
Reset value: 0x0000 30DX
This register contains the control information of each memory bank, used for SRAMs, ROMs
and asynchronous or burst NOR Flash memories.
For Cellular RAM, the bit enables synchronous burst protocol during write operations. For Flash
memory access in burst mode, this bit enables/disables the wait state insertion via the NWAIT
signal. The enable bit for the synchronous burst protocol during read access is the BURSTEN bit in
the FSMC_BCRx register.
0: Write operations are always performed in asynchronous mode
1: Write operations are performed in synchronous mode.
This bit enables the FSMC to program inside the FSMC_BWTR register, so it allows different
timings for read and write.
0: values inside FSMC_BWTR register are not taken into account (default after reset)
1: values inside FSMC_BWTR register are taken into account
For Flash memory access in burst mode, this bit enables/disables wait-state insertion via the
NWAIT signal:
0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the
programmed Flash latency period)
1: NWAIT signal is enabled (its level is taken into account after the programmed Flash latency
period to insert wait states if asserted) (default after reset)
This bit indicates whether write operations are enabled/disabled in the bank by the FSMC:
0: Write operations are disabled in the bank by the FSMC, an AHB error is reported,
1: Write operations are enabled for the bank by the FSMC (default after reset).
For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
by the memory one clock cycle before the wait state or during the wait state:
0: NWAIT signal is active one data cycle before wait state (default after reset),
1: NWAIT signal is active during wait state (not for Cellular RAM).
Reserved
rw
Doc ID 13902 Rev 9
Reserved
15
14 13 12 11 10
rw rw rw rw rw rw rw
9
8
7
rw rw rw rw rw rw rw
6
5
4
3
2
RM0008
1
0