MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 940

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
940/995
Bits 16:14 TTC: Transmit threshold control
Bits 12:8 Reserved
Bit 13 ST: Start/stop transmission
Bit 7 FEF: Forward error frames
Bit 6 FUGF: Forward undersized good frames
Bit 5 Reserved
These three bits control the threshold level of the Transmit FIFO. Transmission starts when the
frame size within the Transmit FIFO is larger than the threshold. In addition, full frames with a
length less than the threshold are also transmitted. These bits are used only when the TSF bit
(Bit 21) is cleared.
When this bit is set, transmission is placed in the Running state, and the DMA checks the
transmit list at the current position for a frame to be transmitted. Descriptor acquisition is
attempted either from the current position in the list, which is the transmit list base address set
by the ETH_DMATDLAR register, or from the position retained when transmission was
stopped previously. If the current descriptor is not owned by the DMA, transmission enters the
Suspended state and the transmit buffer unavailable bit (ETH_DMASR [2]) is set. The Start
Transmission command is effective only when transmission is stopped. If the command is
issued before setting the DMA ETH_DMATDLAR register, the DMA behavior is unpredictable.
When this bit is cleared, the transmission process is placed in the Stopped state after
completing the transmission of the current frame. The next descriptor position in the transmit
list is saved, and becomes the current position when transmission is restarted. The Stop
Transmission command is effective only when the transmission of the current frame is
complete or when the transmission is in the Suspended state.
When this bit is set, all frames except runt error frames are forwarded to the DMA.
When this bit is cleared, the Rx FIFO drops frames with error status (CRC error, collision error,
giant frame, watchdog timeout, overflow). However, if the frame’s start byte (write) pointer is
already transferred to the read controller side (in Threshold mode), then the frames are not
dropped. The Rx FIFO drops the error frames if that frame's start byte is not transferred
(output) on the ARI bus.
When this bit is set, the Rx FIFO forwards undersized frames (frames with no error and length
less than 64 bytes) including pad-bytes and CRC).
When this bit is cleared, the Rx FIFO drops all frames of less than 64 bytes, unless such a
frame has already been transferred due to lower value of receive threshold (e.g., RTC = 01).
000: 64
001: 128
010: 192
011: 256
100: 40
101: 32
110: 24
111: 16
Doc ID 13902 Rev 9
RM0008