MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 509

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
20.9.14
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:24
Reserved
Bits 23:0
SDIO FIFO counter register (SDIO_FIFOCNT)
Address offset: 0x48
Reset value: 0x0000 0000
The SDIO_FIFOCNT register contains the remaining number of words to be written to or
read from the FIFO. The FIFO counter loads the value from the data length register (see
SDIO_DLEN) when the data transfer enable bit, DTEN, is set in the data control register
(SDIO_DCTRL register) and the DPSM is at the Idle state. If the data length is not word-
aligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word.
Bit 6 CMDRENDIE: Command response received interrupt enable
Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable
Bit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable
Bit 3 DTIMEOUTIE: Data timeout interrupt enable
Bit 2 CTIMEOUTIE: Command timeout interrupt enable
Bit 1 DCRCFAILIE: Data CRC fail interrupt enable
Bit 0 CCRCFAILIE: Command CRC fail interrupt enable
Set and cleared by software to enable/disable interrupt caused by receiving command
response.
0: Command response received interrupt disabled
1: command Response Received interrupt enabled
Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.
0: Rx FIFO overrun error interrupt disabled
1: Rx FIFO overrun error interrupt enabled
Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.
0: Tx FIFO underrun error interrupt disabled
1: Tx FIFO underrun error interrupt enabled
Set and cleared by software to enable/disable interrupt caused by data timeout.
0: Data timeout interrupt disabled
1: Data timeout interrupt enabled
Set and cleared by software to enable/disable interrupt caused by command timeout.
0: Command timeout interrupt disabled
1: Command timeout interrupt enabled
Set and cleared by software to enable/disable interrupt caused by data CRC failure.
0: Data CRC fail interrupt disabled
1: Data CRC fail interrupt enabled
Set and cleared by software to enable/disable interrupt caused by command CRC failure.
0: Command CRC fail interrupt disabled
1: Command CRC fail interrupt enabled
Reserved, always read as 0.
FIFOCOUNT: Remaining number of words to be written to or read from the FIFO.
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Doc ID 13902 Rev 9
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Secure digital input/output interface (SDIO)
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