MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 927

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
27.8.3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 31:5 Reserved
Bits 31:0 RGUFC: Received good unicast frames counter
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MMC received good unicast frames counter register (ETH_MMCRGUFCR)
Address offset: 0x01C4
Reset value: 0x0000 0000
This register contains the number of good unicast frames received.
IEEE 1588 time stamp registers
This section describes the registers required to support precision network clock
synchronization functions under the IEEE 1588 standard.
Ethernet PTP time stamp control register (ETH_PTPTSCR)
Address offset: 0x0700
Reset value: 0x0000 0000
This register controls the time stamp generation and update logic.
Bit 5 TSARU: Time stamp addend register update
Bit 4 TSITE: Time stamp interrupt trigger enable
Bit 3 TSSTU: Time stamp system time update
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When this bit is set, the Time stamp addend register’s contents are updated to the PTP block
for fine correction. This bit is cleared when the update is completed. This register bit must be
read as zero before you can set it.
When this bit is set, a time stamp interrupt is generated when the system time becomes greater
than the value written in Target Time register. When the Time Stamp Trigger interrupt is
generated, this bit is cleared.
When this bit is set, the system time is updated (added to or subtracted from) with the value
specified in the Time stamp high update and Time stamp low update registers. Both the
TSSTU and TSSTI bits must be read as zero before you can set this bit. Once the update is
completed in hardware, this bit is cleared.
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Ethernet (ETH): media access control (MAC) with DMA controller
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Reserved
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Doc ID 13902 Rev 9
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RGUFC
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