MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 268

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced-control timers (TIM1&TIM8)
Note:
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For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1.
2.
3.
4.
5.
6.
The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
Figure 74. Control circuit in external clock mode 1
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The
Figure 75. External trigger input block
ETR pin
Figure 75
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
Counter clock = CK_CNT = CK_PSC
ETR
gives an overview of the external trigger input block.
TIMx_SMCR
ETP
0
1
Counter register
/1, /2, /4, /8
ETPS[1:0]
TIMx_SMCR
CNT_EN
Doc ID 13902 Rev 9
divider
TIF
TI2
ETRP
34
f
DTS
Write TIF=0
downcounter
ETF[3:0]
TIMx_SMCR
filter
35
or
(internal clock)
TI2F
TI1F
CK_INT
ETRF
TRGI
or
or
ECE
encoder
mode
external clock
mode 1
external clock
mode 2
internal clock
mode
36
TIMx_SMCR
SMS[2:0]
RM0008
CK_PSC