MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 688

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal synchronous asynchronous receiver transmitter (USART)
25.6.5
688/995
Res.
31
15
LINEN
30
14
rw
Bits 31:15 Reserved, forced by hardware to 0.
Bits 13:12 STOP: STOP bits
Control register 2 (USART_CR2)
Address offset: 0x10
Reset value: 0x0000
Bit 14 LINEN: LIN mode enable
Bit 2 RE: Receiver enable
Bit 1 RWU: Receiver wakeup
Bit 0 SBK: Send break
29
13
rw
STOP[1:0]
Note: 1: Before selecting Mute mode (by setting the RWU bit) the USART must first receive a
Note: The 0.5 Stop bit and 1.5 Stop bit are not available for UART4 & UART5.
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
This bit determines if the USART is in mute mode or not. It is set and cleared by software
and can be cleared by hardware when a wakeup sequence is recognized.
0: Receiver in active mode
1: Receiver in mute mode
This bit set is used to send break characters. It can be set and cleared by software. It should
be set by software, and will be reset by hardware during the stop bit of break.
0: No break character is transmitted
1: Break character will be transmitted
This bit is set and cleared by software.
0: LIN mode disabled
1: LIN mode enabled
The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBK
bit in the USART_CR1 register, and to detect LIN Sync breaks.
These bits are used for programming the stop bits.
00: 1 Stop bit
01: 0.5 Stop bit
10: 2 Stop bits
11: 1.5 Stop bit
28
12
rw
data byte, otherwise it cannot function in Mute mode with wakeup by Idle line detection.
2: In Address Mark Detection wakeup configuration (WAKE bit=1) the RWU bit cannot
be modified by software while the RXNE bit is set.
CLK
EN
27
11
rw
CPOL
26
10
rw
CPHA
25
rw
9
Doc ID 13902 Rev 9
LBCL
24
rw
8
Reserved
Res.
23
7
LBDIE
22
rw
6
LBDL
21
rw
5
Res.
20
rw
4
19
rw
3
18
rw
2
ADD[3:0]
17
rw
1
RM0008
16
rw
0