MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 363

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
14.4.7
Output compare mode
OC2
CE
15
rw
14
rw
Bits 14:12 OC2M[2:0]: Output compare 2 mode
IC2F[3:0]
OC2M[2:0]
TIMx capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
Bit 15 OC2CE: Output compare 2 clear enable
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bit 2 CC2G: Capture/compare 2 generation
Bit 1 CC1G: Capture/compare 1 generation
Bit 0 UG: Update generation
13
rw
refer to CC1G description
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).
12
rw
OC2
IC2PSC[1:0]
PE
11
rw
OC2
FE
10
rw
rw
9
CC2S[1:0]
Doc ID 13902 Rev 9
rw
8
OC1
CE
rw
7
rw
6
IC1F[3:0]
OC1M[2:0]
rw
5
General-purpose timer (TIMx)
rw
4
OC1
IC1PSC[1:0]
PE
rw
3
OC1
FE
rw
2
rw
1
CC1S[1:0]
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rw
0