MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 515

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Note:
21.4
21.4.1
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* Endpoint 0 is always used for control transfer in single-buffer mode.
The USB peripheral is connected to the APB1 bus through an APB1 interface, containing
the following blocks:
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Programming considerations
In the following sections, the expected interactions between the USB peripheral and the
application program are described, in order to ease application software development.
Generic USB device programming
This part describes the main tasks required of the application software in order to obtain
USB compliant behavior. The actions related to the most general USB events are taken into
account and paragraphs are dedicated to the special cases of double-buffered endpoints
and Isochronous transfers. Apart from system reset, action is always initiated by the USB
peripheral, driven by one of the USB events described below.
Control Registers: These are the registers containing information about the status of
the whole USB peripheral and used to force some USB events, such as resume and
power-down.
Interrupt Registers: These contain the Interrupt masks and a record of the events. They
can be used to inquire an interrupt reason, the interrupt status or to clear the status of a
pending interrupt.
Packet Memory: This is the local memory that physically contains the Packet Buffers. It
can be used by the Packet Buffer interface, which creates the data structure and can be
accessed directly by the application software. The size of the Packet Memory is 512
bytes, structured as 256 words by 16 bits.
Arbiter: This block accepts memory requests coming from the APB1 bus and from the
USB interface. It resolves the conflicts by giving priority to APB1 accesses, while
always reserving half of the memory bandwidth to complete all USB transfers. This
time-duplex scheme implements a virtual dual-port SRAM that allows memory access,
while an USB transaction is happening. Multiword APB1 transfers of any length are
also allowed by this scheme.
Register Mapper: This block collects the various byte-wide and bit-wide registers of the
USB peripheral in a structured 16-bit wide word set addressed by the APB1.
APB1 Wrapper: This provides an interface to the APB1 for the memory and register. It
also maps the whole USB peripheral in the APB1 address space.
Interrupt Mapper: This block is used to select how the possible USB events can
generate interrupts and map them to three different lines of the NVIC:
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USB low-priority interrupt (Channel 20): Triggered by all USB events (Correct
transfer, USB reset, etc.). The firmware has to check the interrupt source before
serving the interrupt.
USB high-priority interrupt (Channel 19): Triggered only by a correct transfer event
for isochronous and double-buffer bulk transfer to reach the highest possible
transfer rate.
USB wakeup interrupt (Channel 42): Triggered by the wakeup event from the USB
Suspend mode.
Doc ID 13902 Rev 9
Universal serial bus full-speed device interface (USB)
515/995