MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 888

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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Bits 19:18 Reserved
Bit 21 TER: Transmit end of ring
Bit 20 TCH: Second address chained
Bit 17 TTSS: Transmit time stamp status
Bit 16 IHE: IP header error
Bit 15 ES: Error summary
Bit 14 JT: Jabber timeout
Bit 13 FF: Frame flushed
Bit 12 IPE: IP payload error
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns
to the base address of the list, creating a descriptor ring.
When set, this bit indicates that the second address in the descriptor is the next descriptor
address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16])
is a “don’t care” value. TDES0[21] takes precedence over TDES0[20].
This field is used as a status bit to indicate that a time stamp was captured for the described
transmit frame. When this bit is set, TDES2 and TDES3 have a time stamp value captured for the
transmit frame. This field is only valid when the descriptor’s Last segment control bit (TDES0[29]) is
set.
When set, this bit indicates that the MAC transmitter detected an error in the IP datagram
header. The transmitter checks the header length in the IPv4 packet against the number of
header bytes received from the application and indicates an error status if there is a mismatch.
For IPv6 frames, a header error is reported if the main header length is not 40 bytes.
Furthermore, the Ethernet length/type field value for an IPv4 or IPv6 frame must match the IP
header version received with the packet. For IPv4 frames, an error status is also indicated if
the Header Length field has a value less than 0x5.
Indicates the logical OR of the following bits:
– TDES0[14]: Jabber timeout
– TDES0[13]: Frame flush
– TDES0[11]: Loss of carrier
– TDES0[10]: No carrier
– TDES0[9]: Late collision
– TDES0[8]: Excessive collision
– TDES0[2]:Excessive deferral
– TDES0[1]: Underflow error
– TDES0[16]: IP header error
– TDES0[12]: IP payload error
When set, this bit indicates the MAC transmitter has experienced a jabber timeout. This bit is
only set when the MAC configuration register’s JD bit is not set.
When set, this bit indicates that the DMA/MTL flushed the frame due to a software Flush
command given by the CPU.
When set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP
IP datagram payload. The transmitter checks the payload length received in the IPv4 or IPv6
header against the actual number of TCP, UDP or ICMP packet bytes received from the
application and issues an error status in case of a mismatch.
Doc ID 13902 Rev 9
RM0008