MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 923

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25 24 23 22
Bits 31:22 Reserved
Bits 20:16 Reserved
Bits 16:7 Reserved
Bits 13:0 Reserved
Bits 4:0 Reserved
Ethernet MMC transmit interrupt register (ETH_MMCTIR)
Address offset: 0x0108
Reset value: 0x0000 0000
The Ethernet MMC transmit Interrupt register maintains the interrupts generated when
transmit statistic counters reach half their maximum values. (MSB of the counter is set.) It is
a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that
caused the interrupt is read. The least significant byte lane (bits [7:0]) of the respective
counter must be read in order to clear the interrupt bit.
Reserved
Bit 21 TGFS: Transmitted good frames status
Bit 15 TGFMSCS: Transmitted good frames more single collision status
Bit 14 TGFSCS: Transmitted good frames single collision status
Bit 6 RFAES: Received frames alignment error status
Bit 5 RFCES: Received frames CRC error status
This bit is set when the received frames, with alignment error, counter reaches half the
maximum value.
This bit is set when the received frames, with CRC error, counter reaches half the maximum
value.
This bit is set when the transmitted, good frames, counter reaches half the maximum value.
This bit is set when the transmitted, good frames after more than a single collision, counter
reaches half the maximum value.
This bit is set when the transmitted, good frames after a single collision, counter reaches half
the maximum value.
rc_r
21
Ethernet (ETH): media access control (MAC) with DMA controller
20 19 18 17 16 15
Reserved
Doc ID 13902 Rev 9
rc_r rc_r
14
13 12 11 10
9
8
Reserved
7
6
5
4
3
2
923/995
1
0