MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 687

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bit 11 WAKE: Wakeup method
Bit 10 PCE: Parity control enable
Bit 9 PS: Parity selection
Bit 8 PEIE: PE interrupt enable
Bit 7 TXEIE: TXE interrupt enable
Bit 6 TCIE: Transmission complete interrupt enable
Bit 5 RXNEIE: RXNE interrupt enable
Bit 4 IDLEIE: IDLE interrupt enable
Bit 3 TE: Transmitter enable
Note: 1: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble
This bit determines the USART wakeup method, it is set or cleared by software.
0: Idle Line
1: Address Mark
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
if M=0) and parity is checked on the received data. This bit is set and cleared by software.
Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity will be selected after the current byte.
0: Even parity
1: Odd parity
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever PE=1 in the USART_SR register
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TXE=1 in the USART_SR register
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TC=1 in the USART_SR register
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_SR
register
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever IDLE=1 in the USART_SR register
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
(idle line) after the current word, except in smartcard mode.
2: When TE is set there is a 1 bit-time delay before the transmission starts.
Universal synchronous asynchronous receiver transmitter (USART)
Doc ID 13902 Rev 9
687/995