MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 639

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Note:
24.3.8
24.4
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I
vector.
Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.
Packet error checking
A PEC calculator has been implemented to improve the reliability of communication. The
PEC is calculated by using the C(x) = x
●
●
●
●
●
I
The table below gives the list of I
Table 171. I
2
Start bit sent (Master)
Address sent (Master) or Address matched (Slave)
10-bit header sent (Master)
Stop received (Slave)
Data byte transfer finished
Receive buffer not empty
Transmit buffer empty
2
C interface and DMA generates an interrupt, if enabled, on the DMA channel interrupt
C interrupts
PEC calculation is enabled by setting the ENPEC bit in the I2C_CR1 register. PEC is a
CRC-8 calculated on all message bytes including addresses and R/W bits.
–
–
A PECERR error flag/interrupt is also available in the I2C_SR1 register.
If DMA and PEC calculation are both enabled:-
–
–
To allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register
(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA
request for a master receiver, a NACK is automatically sent after the last received byte.
PEC calculation is corrupted by an arbitration loss.
In transmission: set the PEC transfer bit in the I2C_CR1 register after the TxE
event corresponding to the last byte. The PEC will be transferred after the last
transmitted byte.
In reception: set the PEC bit in the I2C_CR1 register after the RxNE event
corresponding to the last byte so that the receiver sends a NACK if the next
received byte is not equal to the internally calculated PEC. In case of Master-
Receiver, a NACK must follow the PEC whatever the check result. PEC must be
set before the ACK pulse of the current byte reception.
In transmission: when the I
controller, it automatically sends a PEC after the last byte.
In reception: when the I
controller, it will automatically consider the next byte as a PEC and will check it. A
DMA request is generated after PEC reception.
2
C Interrupt requests
Interrupt event
Doc ID 13902 Rev 9
2
2
C interrupt requests.
C interface receives an EOT_1 signal from the DMA
2
C interface receives an EOT signal from the DMA
8
+ x
2
+ x + 1 CRC-8 polynomial serially on each bit.
Event flag
Inter-integrated circuit (I
STOPF
ADD10
ADDR
RxNE
BTF
TxE
SB
ITEVFEN and ITBUFEN
Enable Control bit
ITEVFEN
2
C) interface
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