MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 983

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Table 215. Document revision history (continued)
20-Nov-2007
Date
Revision
2
Figure 238: USART block diagram
Procedure modified in
In
– Equation legend modified
–
– Note added
Small text changes. In
15 is reserved.
Flash memory organization corrected,
(medium-density devices)
memory.
Note added below
supplies.
RTCSEL[1:0] bit description modified in
(RCC_BDCR).
Names of bits [0:2] corrected for RCC_APB1RSTR and RCC_APB1ENR in
Table 15: RCC register map and reset
Impedance value specified in
page
In
BR[2:0] description corrected.
Prescaler buffer behavior specified when an update event occurs (see
upcounting mode on page
Center-aligned mode (up/down counting) on page
AWDCH[4:0] modified in
(ADC_CR1)
time register 1
CAN_BTR bit 8 is reserved in
values.
V
packages on page
Start condition on page 630
alternate function
function
In
(AFIO_MAPR), bit definition modified for USART2_REMAP = 0. In
Section 8.4.3: External interrupt configuration register 1
bit definition modified for SPI1_REMAP = 0.
In
supported.
TRACE port size setting corrected in
page
modified.
Table 8.3.1: Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15
on page 152
Bit descriptions modified in
JTAG ID code corrected in
Modified:
features,
Section 21.3: USB functional
page
ASOE bit description modified in
register
REF+
Table 174: Error calculation for programmed baud rates
Section 25.3.4: Fractional baud rate
Section 23.5.1: SPI control register 1 (SPI_CR1) (not used in I
Section 8.4.2: AF remap and debug I/O configuration register
Table 213: Important TPIU
500.
976.
405,
range corrected in
CAN master control register (CAN_MCR) on page 562
(BKP_RTCCR).
remapping.
Doc ID 13902 Rev 9
Section 5.3.1: Tamper
Figure 14: Basic structure of a five-volt tolerant I/O port bit
Section 18.2: WWDG main
Figure
Section 4.1.2: Battery backup
and bits [26:24] are reserved in
added.
(ADC_SMPR1).
13,
remapping. Note added in
Figure 4: Power supply overview
54.
Figure
Character reception on page
CAN bit timing register (CAN_BTR) on page
Section 11.12.2: ADC control register 1
Table 60: ADC pins
modified in
323,
Section 29.6.2: Boundary scan TAP on page 960
Section 16.4.5
updated. Note removed in
15,
description,
registers, at 0xE0040004, bit2 set is not
A.4: Voltage glitch on ADC input 0 on
Table 164: bxCAN register map and reset
Downcounting mode on page 326
detection,
Figure
Section 5.4.2: RTC clock calibration
Changes
modified.
TPUI TRACE pin assignment on
features,
Section 2.3.3: Embedded Flash
values.
Table 3: Flash module organization
generation:
16,
Backup domain control register
domain,
Controlling the downcounter: on
Section 5.3.2: RTC
and
Figure 17
Section 11.12.4: ADC sample
Table 39: TIM4 alternate
and in
Section 5.2: BKP main
Section
Section 8.2:
328).
On 100-pin and 144- pin
661.
in
and
Section 4.1: Power
Table 30: CAN1
16.4.6.
(AFIO_EXTICR1),
Revision history
Figure 18
modified
calibration,
Introduction.
corrected.
2
S
and
571, bit
mode),
added.
983/995
.