MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 686

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal synchronous asynchronous receiver transmitter (USART)
25.6.3
Note:
25.6.4
686/995
31
15
31
15
rw
Reserved
Res.
30
14
30
14
rw
Bits 31:14 Reserved, forced by hardware to 0.
Bits 31:16 Reserved, forced by hardware to 0.
Bits 15:4 DIV_Mantissa[11:0]: mantissa of USARTDIV
Bits 3:0 DIV_Fraction[3:0]: fraction of USARTDIV
Baud rate register (USART_BRR)
The baud counters stop counting if the TE or RE bits are disabled respectively.
Address offset: 0x08
Reset value: 0x0000
Control register 1 (USART_CR1)
Address offset: 0x0C
Reset value: 0x0000
Bit 13 UE: USART enable
Bit 12 M: Word length
UE
29
13
rw
29
13
rw
Note: The M bit must not be modified during a data transfer (both transmission and
When this bit is cleared the USART prescalers and outputs are stopped and the end of the
current
byte transfer in order to reduce power consumption. This bit is set and cleared by software.
0: USART prescaler and outputs disabled
1: USART enabled
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, n Stop bit
1: 1 Start bit, 9 Data bits, n Stop bit
28
12
rw
These 12 bits define the mantissa of the USART Divider (USARTDIV)
These 4 bits define the fraction of the USART Divider (USARTDIV)
M
28
12
rw
reception)
WAKE
27
11
rw
27
11
rw
DIV_Mantissa[11:0]
PCE
26
10
rw
26
10
rw
PS
25
rw
9
25
rw
9
Doc ID 13902 Rev 9
PEIE
24
rw
24
8
rw
8
Reserved
Reserved
TXEIE
23
rw
23
rw
7
7
TCIE
22
rw
6
22
rw
6
RXNEIE IDLEIE
21
rw
21
rw
5
5
20
rw
20
rw
4
4
19
rw
TE
19
rw
3
3
DIV_Fraction[3:0]
RE
18
rw
18
rw
2
2
RWU
17
rw
17
rw
1
1
RM0008
SBK
16
rw
16
rw
0
0