MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 63

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bits 7:5 PLS[2:0]: PVD level selection.
Bit 8 DBP: Disable backup domain write protection.
Bit 4 PVDE: Power voltage detector enable.
Bit 3 CSBF: Clear standby flag.
Bit 2 CWUF: Clear wakeup flag.
Bit 1 PDDS: Power down deepsleep.
Bit 0 LPDS: Low-power deepsleep.
Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.
These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector
Note: Refer to the electrical characteristics of the datasheet for more details.
This bit is set and cleared by software.
This bit is always read as 0.
This bit is always read as 0.
This bit is set and cleared by software. It works together with the LPDS bit.
This bit is set and cleared by software. It works together with the PDDS bit.
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
000: 2.2V
001: 2.3V
010: 2.4V
011: 2.5V
100: 2.6V
101: 2.7V
110: 2.8V
111: 2.9V
0: PVD disabled
1: PVD enabled
0: No effect
1: Clear the SBF Standby Flag (write).
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
Doc ID 13902 Rev 9
Power control (PWR)
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