MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 271

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
13.3.6
Figure 79. Output stage of capture/compare channel (channel 1 to 3)
Figure 80. Output stage of capture/compare channel (channel 4)
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
CNT > CCR4
CNT = CCR4
CNT>CCR1
CNT=CCR1
ETR
ETR
OC1CE
Output mode
OC2M[2:0]
TIM1_CCMR2
Output mode
controller
TIM1_CCMR1
controller
OC1M[2:0]
OC4 REF
OC1REF
Doc ID 13902 Rev 9
Dead-time
generator
TIM1_BDTR
DTG[7:0]
To the master mode
controller
OC1N_DT
OC1_DT
CC1NE
‘0’
‘0’
TIM1_CCER
Advanced-control timers (TIM1&TIM8)
x0
10
11
11
10
0x
CC1E
TIM1_CCER
CC4P
TIM1_CCER
TIM1_CCER
CC1NP
0
1
CC1P
0
1
0
1
MOE
MOE
CC1NE
Output
enable
circuit
CC4E TIM1_CCER
OIS4
OSSI
Output
enable
Output
enable
circuit
circuit
OSSI TIM1_BDTR
CC1E TIM1_CCER
OSSR
TIM1_CR2
OC4
TIM1_BDTR
OC1N
OC1
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