MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 911

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved
Bits 15:11 PA: PHY address
Bits 31:0 HTL: Hash table low
Bits 10:6 MR: MII register
Bits 4:2 CR: Clock range
Ethernet MAC hash table low register (ETH_MACHTLR)
Address offset: 0x000C
Reset value: 0x0000 0000
The Hash table low register contains the lower 32 bits of the multi-cast Hash table.
Ethernet MAC MII address register (ETH_MACMIIAR)
Address offset: 0x0010
Reset value: 0x0000 0000
The MII address register controls the management cycles to the external PHY through the
management interface.
Bit 5 Reserved
Bit 1 MW: MII write
This field contains the lower 32 bits of the Hash table.
This field tells which of the 32 possible PHY devices are being accessed.
These bits select the desired MII register in the selected PHY device.
The CR clock range selection determines the HCLK frequency and is used to decide the
frequency of the MDC clock:
When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If
this bit is not set, this will be a Read operation, placing the data in the MII Data register.
Selection
000
001
010
011
100, 101, 110, 111 Reserved
Reserved
Ethernet (ETH): media access control (MAC) with DMA controller
HCLK
60-72 MHz
Reserved
20-35 MHz
35-60 MHz
Doc ID 13902 Rev 9
HTL
rw rw rw rw rw rw rw rw rw rw
MDC Clock
HCLK/42
-
HCLK/16
HCLK/26
-
PA
9
9
MR
8
8
7
7
6
6
5
5
rw rw rw
4
4
CR
3
3
2
2
911/995
MW MB
rw
1
1
rc_
w1
0
0